Hardware and Interrupts

1. Basic overview of hardware
1. CPU connected to a system bus with a memory controller and several I/O controllers.
2. Devices also connected to CPU via interrupt lines.
3. CPU and device talk via shared memory
4. Devices can request the CPU's attention via an interrupt
5. CPU can request the device's attention via writing to a special part of 'memory'.
6. Other models are possible.
2. Interrupts
1. Definition -- async hardware event causing change in CPU flow of control.
2. Types
1. Processor exception
1. Error (division by zero, illegal instruction)
2. Normal (VM page missing, emulated instructions)
2. Software (some CPUs use for system calls)
1. synonym for TRAP
3. Generated by a device
1. I/O completion (not normally I/O start)
2. Clock timer. (Time of day, scheduling)
3. Attributes
1. Possibly Maskable
2. Maximum latency allowed
3. Possibly Shared
3. Interrupt handling
1. Interrupt table in RAM
1.  Save enough info to be able to restart
1. put on stack (yours or a fixed stack or system stack)
2. Normally interrupt code must save registers
2. Modern RISC is to make interrupt spill hard to understand
2. Exec interrupt routine
1. Maybe some service is required (process uses an interrupt to make a system call, instruction emulation?)
2. Maybe handled a problem (access to non-existant memory address, divide by zero, illegal instruction)
3. Maybe device wanted attention (IO is finished, timer went off)
   
3. Resume execution
4. Interrupt Priority
1. Often interrupts DISABLE other interrupts
1. this function built into hardware to avoid race condition
2. Disabled interrupts are often MISSED but sometimes DELAYED/QUEUED
3. Sometimes interrupts disabled for O.S. needs
4. changing important system table, SMP needs, etc.
5. Can screw I/O if disabled for two long.
2. Some interrupts cannot be disabled (NMI, clock, page fault).