Chapter 2 -- Computer System Structure

Hardware and Interrupts

  1. Basic overview of hardware
    1. CPU connected to a system bus with a memory controller and several I/O controllers.
    2. Devices also connected to CPU via interrupt lines.
    3. CPU and device talk via shared memory
    4. Devices can request the CPU's attention via an interrupt
    5. CPU can request the device's attention via writing to a special part of 'memory'.
    6. Other models are possible.
  2. Interrupts
    1. Definition -- asynch hardware event causing change in CPU flow of control.
    2. Types
      1. Processor exception
        1. Error (division by zero, illegal instruction)
        2. Normal (VM page missing, emulated instructions)
      2. Software (some CPUs use for system calls)
        1. synonym for TRAP
      3. Generated by a device
        1. I/O completion (not normally I/O start)
        2. Clock timer. (Time of day, scheduling)
    3. Attributes
      1. Maskable??
      2. Maximum latency allowed
      3. Shared?
  3. Interrupt handling
    1. Interrupt table in RAM
      1.  Save enough info to be able to restart
        1. put on stack (yours or a fixed one or system)
        2. Normally interrupt code must save registers
      2. Modern RISC is to make interrupt spill hard to understand
    2. Exec interrupt routine
      1. Maybe did some service (I/O, instruction emulation?)
      2. Maybe handled a problem (VM, divide by zero??)
      3. Maybe killed process
    3. Resume execution
    4. Interrupt Priority
      1. Often interrupts DISABLE other interrupts
        1. this function built into hardware to avoid race condition
        2. Disabled interrupts are often MISSED but sometimes DELAYED/QUEUED
        3. Sometimes interrupts disabled for O.S. needs
        4. changing important system table, SMP needs, etc.
        5. Can screw I/O if disabled for two long.
      2. Some interrupts cannot be disabled (NMI, clock, page fault).

Memory and Storage Hierarchy

        - Memory Hierarchy
                - Memory goals
                        - Free
                        - Fast
                        - Nonvolatile
                        - Portable
                        - Random access
                - Hierarchy
                        CPU registers  -- access in nanoseconds
                        CPU Cache      -- access in 10 nanoseconds
                        Second level cache -- access in 30 nanoseconds
                        Main memory    -- access in 100 nanoseconds
                        Electronic disk   -- access in 100 nanoseconds
                                - useful to overcome address space limits
                                - can use cheap RAM
                        Magnetic disk -- access in 10,000 nanoseconds
                                - describe track/sector/platter/cylindar
                                - Can have a change media event
                                - normally sector write is atomic
                                - hard drive heads float, floppy heads ride surface
                        Magnetic tape -- access in 10's of seconds
                                - Can have a change media event
                                - have blocks (like sector) can have track.
                                - explain helix scan
                - VM stored on levels down to mag disk
               - Files stored on levels up to electronic disk.

                - Caching Problems
                        - Different apps on same CPU can read different values for the same variable
                        - Different CPUs can read different values for the same RAM location. -- this must be fixed!
                        - After media switch, caching can cause WRONG values to be read from floppy disk or tape.

I/O System Calls

         - I/O structure
                - Controllers
                        - hardware
                                - Load control registers
                                - Access the "go" register.
                                - Await interrupt.
                                - Sometimes controller can do DMA
                                - Sometimes controller has internal buffers.
                - O.S. structure: synchronous
                        - App does something (I/O request, VM, etc.).
                        - O.S. gets system call, translates into device I/O.
                        - device driver translates I/O into "dev-speak".
                        - wait to I/O to complete (jmp to self)
                        - O.S. gets interrupt, gives control to device driver
                        - Driver copies/moves data, sets completion flag
                        - Process continues
                        - ADVANTAGE: Simple
                        - DISADVANTAGE: no overlapping I/O and computation
                - O.S. structure: Asynchronous
                        - App does something (I/O request, VM, etc.).
                        - O.S. gets system call, translates into device I/O.
                        - device driver translates I/O into "dev-speak".
                        - Another process continues
                        - O.S. gets interrupt, gives control to device driver
                        - Driver copies/moves data, sets completion flag
                        - Scheduler notices flag, allows original process to continue
                        - ADVANTAGE: Overlapping computation and I/O
                        - DISADVANTAGE: complex, need more than one app for overlap
                - O.S. structure: Application Asynchronous
                        - App does something (I/O request, VM, etc.).
                        - O.S. gets system call, translates into device I/O.
                        - device driver translates I/O into "dev-speak".
                        - Original application continues (subject to scheduling)
                        - O.S. gets interrupt, gives control to device driver
                        - Driver copies/moves data
                                - Driver can notify app, --OR--
                                - Driver notifies O.S., which tells app
                        - ADVANTAGE: single apps can overlap I/O and computation
                        - DISADVANTAGE: I/O interface becomes complex
                - O.S. structure: device driven
                        - Device generates interrupt with data ready
                        - Data stored in buffer (if room)
                        - When app requests, data presented)
                - Device driver structure
                        - regular interface for ease of programming
                                - list standard operations (init, r/w, stat, change media)
                                - Sometimes classes (block, char)
                        - Often have top (start request) and bottom (interrupt driven) halves.
                        - Can have multiple outstanding requests
                                - Keep list
                                - Sort list??
 
 

        - Hardware protection needed for security from bad apps
                - Memory protection
                        - interrupt handler
                        - OS code
                        - OS data
                        - OS stack
                        - memory mapped devices
                        - memory given to other applications
                - CPU protection
                        - Keep users out of kernel CPU mode.
                        - don't allow users to access the MMU.
                        - All very long running instructions (shift, pointer-follow, vector-op) must be interruptable.
                - Timer protection

        Good questions: 2.4, 2.5, 2.6, 2.7 2.8, 2.9, 2.10