Computer Hardware

Basic overview of hardware
	- CPU connected to a system bus with a memory controller and several I/O controllers.
		- Integer programming becoming limited by memory speed.
			- Cost of Cray not in CPU, but in memory subsystem.
			- CPUs have very expensive caches to help
				- Only help if locality
				- O.S.'s tend to bust locality.
		- Graphics can be limited by memory speed.
			- High frame update rate
			- Poor locality.
			- Important performance criterea.
		- SCSI is very common.
			- Can connect many things (tape, disk, scanners).
			- Only need one type of device driver.

	- Memory Heirarchy
		- Memory goals
			- Free
			- Fast
			- Non-volitile
			- Portable
			- Random access
		- Heirarchy
			CPU registers
			CPU Cache
			Second level cache
			Main memory
			Electronic disk 
				- useful to overcome address space limits
				- can use cheap RAM
			Magnetic disk
				- describe track/sector/platter/cylendar
				- Can have a change media event
				- normally sector write is atomic
				- hard drive heads float, floppy heads ride surface
			Magnetic tape
				- Can have a change media event
				- have blocks (like sector) can have track.
				- explain helix scan
		- VM stored on levels down to mag disk
		- Files stored on levels up to electronic disk.

		- Caching Problems
			- Different apps on same CPU can read different values for the same variable
			- Different CPUs can read different values for the sam RAM location.
			- After media switch, caching can cause WRONG values to be read from floppy disk.


	- Interrupts
		- Interrupt attributes
			- Definition -- asynch external hardware event causing change
			in CPU flow of control.
			- Types
				- Hardware 
					- I/O completion (not normally I/O start)
					- Clock timer. (Time of day, scheduling)
					- Processor exception
						- Error (division by zero, illegal instruction)
						- Normal (VM page missing, emulated instructions)
				- Software (some CPUs use for system calls)
					- synomyn for TRAP
			- Attributes
				- Maskable??
				- Maximum latency allowed
				- Shared?
	
		- Interrupt handling
			- Interrrupt table in RAM
			- Save enough info to be able to restart
				- put on stack (yours or a fixed one or system)
				- Normally interrupt code must save registers
				- Modern RISC is to make interupt spill hard to understand
			- Exec interrupt routine
			- Resume execution
				- Maybe did some service (I/O, instruction emulation?)
				- Maybe handled a problem (VM, divide by zero??)
				- Maybe killed process
		- Interrupt Priority
			- Often interrupts DISABLE other interrupts
				- this function built into hardware to avoid race condition
			- Disabled interrupts are often MISSED but sometimes DELAYED/QUEUED
			- Some interrupts cannot be disabled (NMI, clock, page fault).
				- Make sure these are avoided.
				- make sure handler in re-enterent.
			- Sometimes interrupts disabled for O.S. needs
				- changing important system table, SMP needs, etc.
				- Can screw I/O if disabled for two long.

	- Device drivers
		- regular interface for ease of programming
			- list standard operations (init, r/w, stat, change media)
			- Sometimes classes (block, char)
		- Often have top (start request) and bottom (interrupt driven) halves.
		- Can have multiple outstanding requests
			- Keep list
			- Sort list??
		-Starting an I/O operation
			- Load control registers
			- Access the "go" register.
		-Noticing when an operation is finished
			- When interrupt happens
				-Data is available
					- Sometimes controller can do DMA (otherwise it's in an internal buffer)
					- Sometimes you must copy the data (ick)			
				-Ready for next operation if there is one already to go



	- Hardware protection needed for security from bad apps
		- Memory protection
			- interrupt handler
			- OS code
			- OS data
			- OS stack
			- memory mapped devices
			- memory given to other applications
		- CPU protection
			- Keep users out of kernel CPU mode.
			- don't allow users to access the MMU.
			- All very long running instructions (shift, pointer-follow, vector-op) must be interruptable.
		- Timer protection